1. Field of the Invention
The present invention generally relates to internal power supply circuits, and more particularly, to an improvement of an internal power supply circuit generating an internal power supply potential based on an external power supply potential for an internal circuit in a semiconductor memory device.
2. Description of the Background Art
With recent progress of miniaturization of a semiconductor integrated circuit device, an internal power supply potential (for example, 3 V) lower than an external power supply potential (for example 5 V) is supplied to its internal circuit. In such a semiconductor integrated circuit device, only when the internal circuit is activated, current required for the internal circuit is supplied in order to reduce power consumption. More specifically, when the internal circuit is not activated, only current required for a stand-by state is supplied.
FIG. 8 is a block diagram showing a conventional internal power supply circuit supplying an internal power supply potential to a sense amplifier driving circuit and its peripheral circuit of a dynamic random access memory
Referring to FIG. 8, an internal power supply circuit 1 includes an output node 2 connected to a power supply node of the peripheral circuit, an output node 3 connected to a power supply node of the sense amplifier driving circuit, a down converter 4 for the peripheral circuit generating an internal power supply potential intVcc based on an external power supply potential extVcc, and a down converter 5 for the sense amplifier driving circuit generating the internal power supply potential intVcc based on the external power supply potential extVcc.
Down converter 4 includes a primary internal power supply potential supplying circuit 6 and an auxiliary internal power supply potential supplying circuit 7. Primary internal power supply potential supplying circuit 6 supplies, based on the external power supply potential extVcc, the internal power supply potential intVcc lower than the same to output node 2. Auxiliary internal power supply potential supplying circuit 7 is activated in response to a control signal .phi.1, and, when activated, supplies the internal power supply potential intVcc to output node 2 based on the external power supply potential extVcc.
Similar to down converter 4, down converter 5 includes a primary internal power supply potential supplying circuit 8, and an auxiliary internal power supply potential supplying circuit 9. Similar to primary internal power supply potential supplying circuit 6, primary internal power supply potential supplying circuit 8 supplies the internal power supply potential to output node 3 based on the external power supply potential extVcc. Similar to auxiliary internal power supply potential supplying circuit 7, auxiliary internal power supply potential supplying circuit 9 is activated in response to a control signal .phi.2, and, when activated, supplies the internal power supply potential intVcc to output node 3 based on the external power supply potential extVcc.
Description will now be given of operation of internal power supply circuit 1.
In a stand-by state, the control signals .phi.1 and .phi.2 both at an L level are applied to auxiliary internal power supply potential supplying circuits 7 and 9, respectively. The L level denotes a low logic level.
When the control signals .phi.1 and .phi.2 at the L level are applied, auxiliary internal power supply potential supplying circuits 7 and 9 do not generate the internal power supply potential intVcc. On the other hand, primary internal power supply potential supplying circuits 6 and 8 always generate the internal power supply potential intVcc independent of the control signals .phi.1 and .phi.2.
Therefore, in the stand-by state, the internal power supply potential intVcc is supplied to the peripheral circuit through output node 2 only by primary internal power supply potential supplying circuit 6 in down converter 4. Since the peripheral circuit is in the stand-by state at this time, little power is consumed. Therefore, it is sufficient to have a driving ability of primary internal power supply potential supplying circuit 6 smaller than that of auxiliary internal power supply potential supplying circuit 7.
In the stand-by state, the internal power supply potential intVcc is supplied to the sense amplifier driving circuit through output node 3 only by primary internal power supply potential supplying circuit 8 in down converter 5. Since the sense amplifier driving circuit is in the stand-by state at this time, little power is consumed. Therefore, it is sufficient to have a driving ability of primary internal power supply potential supplying circuit 8 smaller than that of auxiliary internal power supply potential supplying circuit 9.
As described above, in the stand-by state, the internal power supply potential intVcc is supplied to the peripheral circuit through output node 2 by primary internal power supply potential supplying circuit 6 having a small driving ability, and to the sense amplifier driving circuit through output node 3 by primary internal power supply potential supplying circuit 8 having a small driving ability. Therefore, power consumed in the standby state becomes very small.
In an active state, in response to the falling of a row address strobe signal RAS (not shown), the internal circuit of the DRAM starts to operate. In response to the falling of the row address strobe signal RAS, the control signals .phi.1 and .phi.2 rise from the L level to an H level. The H level denotes a high logic level. In response to the control signal .phi.1 at the H level, auxiliary internal power supply potential supplying circuit 7 is activated, causing the internal power supply potential intVcc to be supplied to the peripheral circuit through output node 2.
On the other hand, in response to the control signal .phi.2 at the H level, auxiliary internal power supply potential supplying circuit 9 is activated, causing the internal power supply potential intVcc to be supplied to the sense amplifier driving circuit through output node 3.
As described above, in the active state, the internal power supply potential intVcc is supplied to the peripheral circuit also by auxiliary internal power supply potential supplying circuit 7 having a large driving ability. Similarly, the internal power supply potential intVcc is supplied to the sense amplifier driving circuit also by auxiliary internal power supply potential supplying circuit 9 having a large driving ability. Therefore, the peripheral circuit and the sense amplifier driving circuit operate stably.
Since a number of sense amplifiers are driven in the active state, more power is consumed in the sense amplifier driving circuit than in the peripheral circuit. Therefore, upon driving of the sense amplifiers, the potential of output node 3 sometimes changes sharply. Since down converter 4 and down converter 5 are provided independently in internal power supply circuit 1, such a potential change of output node 3 as described above has no influence on output node 2.
Since two down converters 4 and 5 are provided in internal power supply circuit 1, however, power consumption becomes larger that the case where one down converter is provided.